Semiconductor non-volatile memories have been more and more miniaturized and the capacity thereof has been increased. However, it has not been possible to miniaturize semiconductor non-volatile memories in accordance with the scaling law, and the cell current in the smallest cell has been decreasing. Therefore, with semiconductor non-volatile memories, there is a need for a method for sensing memory cells at a high speed and with a high sensitivity.
While the cell current decreases, the memory capacity required for a system has been increasing at a speed greater than that of miniaturization, whereby the mat size of the array in which memory cells are arranged has been increasing. There is no problem if the capacitance of bit lines, etc., decreases as the miniaturization proceeds. In fact, however, the miniaturization of the memory cell size has slowed down, with the fringe capacitance in the lateral direction of the bit line having increased, and this, combined with the increase in the array mat size, leads to an increase in the bit line capacitance. An increase in the bit line capacitance may cause problems for a sensing operation with a high sensitivity.
Moreover, it is necessary to maintain an access speed even when the memory capacity increases. Therefore, there is a need for a sense amplifier and a sensing method that are faster and more sensitive in order to maintain the access speed.
For example, the VGA (Virtual Ground Array Architecture) structure is well known in the art as an array architecture that is suitable for high degree of integration for a semiconductor non-volatile memory, and various techniques have been developed for maintaining the symmetry of the differential input as much as possible by using the differential-amplification type sense amplifier in order to increase the sensing operation of the array of the VGA structure.
Specifically, a method has been proposed in the art, in which a folded bit line arrangement is employed for bit lines so that the bit line-reference bit line distance is significantly shortened as compared with the previous open bit line arrangement, whereby the electric characteristics are unlikely to fall out of balance and the noise voltage introduced to the wire pair from other conductors such as peripheral circuits is made as uniform as possible (see, for example, Patent Document 1).
FIG. 18 is a block diagram showing a configuration of a conventional semiconductor non-volatile memory 4000. As shown in FIG. 18, the semiconductor non-volatile memory 4000 includes memory cells, bit lines BL, word lines WL, reference bit lines BLR, a Y decoder 4001, a reference unit 4002, and a sense amplifier 4003.
The memory cells are arranged in a matrix pattern. The bit lines BL extend between columns of the memory cells arranged in a matrix pattern, and the word lines WL extend between rows of the memory cells arranged in a matrix pattern.
The reference bit lines BLR are lines provided so as to receive an equal level of noise, etc., to that on the memory cell side in a data read operation, and have an equal level of parasitic capacitance thereon to the parasitic capacitance on the bit lines BL. Normally, the reference bit line BLR is provided for each sense amplifier (a plurality of sense amplifiers share a reference bit line in some cases). Each reference bit line BLR and a bit line BL being the counterpart thereto are laid out close to each other in a pattern in which a relatively high level of symmetry is maintained.
The Y decoder 4001 connects the bit line BL, to which memory cells are connected, to the sense amplifier 4003.
The reference unit 4002 produces the reference voltage Vref to be used by the sense amplifier 4003.
The sense amplifier 4003 amplifies the voltage difference between the voltage Vcell of the bit line BL, which is connected thereto by the Y decoder 4001, and the reference voltage Vref being the reference.
When data is read out from a memory cell in the semiconductor non-volatile memory 4000 having such a configuration, data stored in the memory cell is first read out by using two bit lines BL connected to the diffusion layer of the memory cell being read out and a word line WL connected to the gate thereof, and the voltage Vcell of the bit line BL connected to the drain side is output to the Y decoder 4001. The Y decoder 4001 outputs the voltage Vcell of a bit line BL that is connected to the drain side to the sense amplifier 4003.
The reference unit 4002 produces the reference voltage Vref, and outputs the produced reference voltage Vref to the sense amplifier 4003. Two reference bit lines BLR are selected and connected to the reference unit 4002.
Thus, the parasitic capacitance on the bit line BL connected to the memory cell from which data is being read out becomes equal to the parasitic capacitance on the reference bit line BLR connected to the reference unit 4002. In other words, the capacitance balance between the bit line BL and the reference bit line BLR is maintained, whereby each pair of bit lines receives a substantially equal level of noise. As a result, the difference between the signal read out from the memory cell and the signal read out from the reference unit is dependent substantially only on the cell current difference, which is suitable for differential amplification.
Patent Document 1: U.S. Pat. No. 6,128,226 (Page 1, FIG. 1)